With the progress of technology, semiconductor device geometries are being continually scaled down. As the device geometries are scaled down, so are the thin isolation or oxide layers of the devices. Thus, to accommodate the smaller sized devices, the supply voltages have been necessarily reduced from the standard 5.0 volts to 3.3 volts, and in some instances smaller supply voltages are used, such as 2.5 volts and 1.8 volts.
Integrated circuits typically contain devices that are designed to use a standard 5.0 volt supply voltage as well as devices that are designed for the lower supply voltages. For example, CMOS logic gates in the core of the chip use a low supply voltage, while devices on the perimeter of the chip and external to the chip use a high supply voltage. Where high voltage devices are used in conjunction with low voltage devices, the low voltage devices may encounter over voltages causing excessive voltage stresses in the thin insulation or oxide layers thereby damaging the devices. Consequently, the low voltage devices used in the chip must be protected from the higher voltage supplies used by devices on and external to the chip.
High voltage buffers are used to interface the core circuitry in the chip, with the high voltage devices on the chip or the external environment. Conventionally, complicated circuitry or complicated device processing are used to generate high voltage buffers on low voltage circuitry. For example, a conventional method of protecting devices from over voltage is to grow a thick oxide layer on the device so that the device can tolerate a higher voltage. However, growing a thicker oxide on a device requires additional complicated processing, thus decreasing yield and increasing cost.